1. Field of the Invention
The present invention relates to the structure of a data output circuit of a semiconductor memory device.
2. Description of the Background Art
In accordance with the increase in speed of recent systems, high speed operation is required even for the dynamic type semiconductor memory device incorporated in the system. Practical application of a synchronous type semiconductor memory device and the like is in progress.
A trend is towards increasing the bit width in the data input/output of a semiconductor memory device for the purpose of providing flexibility in designing the system that incorporates the semiconductor memory device and reducing the size of the system.
In other words, when the semiconductor memory device includes n (n: natural number) data input/output terminals and data is received or sent with respect to an external source through the n data input/output terminals, the trend of increase in the number of the n data input/output terminals is identifiable.
FIG. 7 is a schematic block diagram showing a structure of an output circuit 800 controlling the data output timing in a conventional semiconductor memory device.
Output circuit 800 includes an output control signal generation circuit 810 receiving external control signals such as a row address strobe signal/RAS, a column address strobe signal/CAS, an output enable signal/OE and a write enable signal/WE and generating an output control signal OEM when data output is specified by a certain combination of these control signals, and a timing control circuit 820 receiving output control signal OEM to generate a signal VPO to control the data output timing.
Timing control circuit 820 includes a high voltage generation circuit 822 receiving an external power supply voltage Vcc and a ground potential GND to generate a high voltage Vpp used in data output, and an output control circuit 824 receiving the output of high voltage generation circuit 822 to output an output activation control signal VPO having an activation level that corresponds to high voltage Vpp in response to activation of output control signal OEM.
Output circuit 800 further includes output circuits 840.1.about.840.n provided corresponding to data input/output terminals DQ0.about.DQn-1, respectively, having the timing controlled by output activation control signal VPO to drive the potential level of corresponding data input/output terminals DQ0.about.DQn-1 according to received readout data RD0.about.RDn-1, respectively.
By the above structure, data RD0.about.RDn read out from a memory cell array (not shown) can be output to data input/output terminals DQ0.about.DQn-1 at one time.
It is to be noted that the structure shown in FIG. 7 has the plurality of output circuits controlled by timing control circuit 820. Therefore, there was a problem that the period of time of data being actually output in response to designation of data output by the external control signal becomes longer as the number of data input/output terminals DQ0.about.DQn-1 is increased.